1. Technical Field
The embodiment described herein relates to a semiconductor memory apparatus and, more particularly, to a bit line precharge circuit that precharges a bit line and a semiconductor memory device using the same.
2. Related Art
A semiconductor memory apparatus performs an active operation and then perform a precharge operation in order to perform a subsequent active operation. In general, when a precharge command is inputted, the precharge operation is performed and a pair of bit lines BL and /BL that are amplified to a core voltage VCORE and a ground voltage VSS respectively, are sustained to a bit line precharge voltage VBLP (a half of the voltage level of the core voltage).
FIG. 1 is a diagram illustrating a schematic configuration of a conventional bit line precharge circuit. The precharge circuit 10 includes first to third NMOS transistors N1, N2, and N3. The first NMOS transistor N1 connects the bit lines BL and /BL to each other when a bit line equalizing signal ‘BLEQ’ is enabled. The second and third NMOS transistors N2 and N3 sustain voltage levels of the pair of bit lines BL and /BL to the level of the bit line precharge voltage VBLP when the bit line equalizing signal ‘BLEQ’ is enabled. The bit line equalizing signal ‘BLEQ’ is generated in the semiconductor memory apparatus to be enabled when the precharge command is inputted and disabled when an active command is inputted in order to precharge the pair of bit lines BL and /BL. In FIG. 1, a short fail occurs between a word line WL and a bit line BL. The short fail may occur while the semiconductor memory apparatus is highly integrated and means that an unwanted bridge occurs between the bit line BL and the word line WL. When the short fail occurs, a leakage current is generated from the bit line BL that is precharged at the level of the bit line precharge voltage VBLP to the word line WL of the level of the ground voltage VSS. The leakage current is also referred to as a bleed current. When the bleed current increases, the voltage level of the bit line BL decreases, such that a subsequent active operation cannot be performed normally.
In order to solve the above-mentioned problem, a precharge method using a bleeder transistor has been developed. FIG. 2 is a diagram illustrating a schematic configuration of a bit line precharge circuit in another conventional art. The bit line precharge circuit 20 includes fourth to sixth NMOS transistors N4 to N6 and a bleeder NMOS transistor NB. In another conventional art, a bit line precharge voltage VBLP is not applied directly to a pair of bit lines BL and /BL but the bit line precharge voltage VBLP is applied to the pair of bit lines BL and /BL through the bleeder transistor NB. That is, the bleeder transistor NB is constituted by a transistor having a comparatively long channel length to decrease a current supply amount to the pair of bit lines BL and /BL through the bleeder transistor NB. Accordingly, the leakage current generated from the bit line BL to the word line WL remarkably decreases.
However, in said another conventional art, the ability to supply the bit line precharge voltage VBLP to the pair of bit lines BL and /BL is reduced, such that a precharge characteristic is deteriorated and an operation speed of the semiconductor memory apparatus decreases.